Bus

/eɪtʃ diː aɪ ɛm aɪ/

n. "Proprietary audio/video interface carrying TMDS streams with CEC unlike royalty-free DisplayPort."

HDMI, short for High-Definition Multimedia Interface, transmits uncompressed video, multi-channel audio, and control data over TMDS lanes (HDMI2.1=48Gbps), supporting 10K@120Hz with DSC, ARC/eARC return audio, and CEC device control across Type-A/D/Mini/Micro connectors. Unlike DVI's video-only limitation, HDMI embeds DD++/EDID, Consumer Electronics Control (CEC=BraviaSync), and Audio Return Channel (ARC) in blanking intervals, with licensing fees funding HDMI Forum evolution contrasting VESA's open DisplayPort.

Key characteristics of HDMI include: TMDS Encoding 8b→10b like DVI but with audio/infoframes (HDMI2.1=12/24Gbps TMDS x3 lanes); HDR10/HLG/Dolby Vision dynamic metadata; eARC bidirectional 37Mbps uncompressed audio (Dolby TrueHD); Variable Refresh Rate (VRR=FreeSync); Source-Based Tone Mapping for mismatched dynamic range; Ultra High Speed cables mandatory for 48Gbps (48Gbps active optical).

Conceptual example of HDMI usage:

/* HDMI 2.1 Source InfoFrame packet for 4K@120Hz HDR */
struct hdmi_infoframe {
    uint8_t type = 0x87;          // AVI InfoFrame
    uint8_t version = 0x02;
    uint8_t length = 0x0D;
    uint8_t checksum;
    
    // Video ID Code (VIC) for 4K120
    uint8_t vic = 97;             // 3840x2160@120Hz
    uint8_t pixel_repeat = 0;
    
    // Colorimetry + Dynamic Range
    uint8_t colorimetry = 0x04;   // BT.2020
    uint8_t dynamic_range = 0x01; // HDR Static Metadata Type 1
} avi_if;

void hdmi_send_infoframe(struct hdmi_infoframe *ifp) {
    calculate_checksum(ifp);
    tmds_insert_during_blanking(ifp, HDMI_PACKET_PERIOD);
}

Conceptually, HDMI bundles pixel clock+TMDS data lanes with sideband packets during blanking (like DisplayPort MSA but HDMI-licensed), tunneling through USB4 ALT mode while CEC chains Blu-ray→soundbar→TV control. HDMI2.1 FRL (Fixed Rate Link) replaces TMDS for 48Gbps, stress-tested via PRBS patterns hitting receiver CTLE/DFE, with Ultra High Speed cables ensuring 1e-12 BER unlike passive copper limits plaguing early HDMI2.0 18Gbps deployments.

/ˌdiː ɛs ˈsiː/

n. "VESA's visually lossless video compression enabling 8K@60Hz over DisplayPort HBR3 bandwidth limits."

DSC, short for Display Stream Compression, is a low-latency compression algorithm developed by VESA that achieves 3:1 ratios using DPCM prediction, YCoCg-R color transform, and entropy coding on pixel slices, enabling 4K@144Hz/8K@60Hz over existing DisplayPort 1.4 (25.92Gbps) and HDMI 2.1 links without perceptible artifacts. Processes frames in real-time (sub-microsecond latency) by dividing into independent slices (1/3-1/4 frame width), quantizing residuals after intra prediction—mandatory for USB4 UHBR20 tunnels exceeding raw pixel clocks.

Key characteristics of DSC include: Visually Lossless 3:1 compression (119Gbps 8K@60 → 40Gbps) imperceptible at normal viewing distances; Zero Latency real-time encoding/decoding (<1μs end-to-end); Slice-Based parallel processing of 1/3 frame widths with independent headers; YCoCg-R Color optimal for luma/chroma separation unlike RGB quantization; Rate Control maintains constant bitrate via qp adjustment without buffering.

Conceptual example of DSC usage:

/* DSC 1.2a encoder slice processing */
typedef struct {
    uint32_t slice_width;    // 1/3 frame width (e.g. 1280 for 3840x2160)
    uint32_t slice_height;   // 8-108 lines
    int qp;                  // Quantization parameter [8-17]
    bool intra_mode;         // Force all-intra slice
} dsc_slice_config;

void dsc_encode_slice(uint16_t *rgb_pixels, uint8_t *compressed) {
    // 1. YCoCg-R color transform
    int16_t y, co, cg, r;
    y  = (rgb >> 2) + (rgb >> 1) + (rgb >> 2); [youtube](https://www.youtube.com)
    co = (rgb >> 1) - (rgb >> 1);
    cg = (rgb >> 1) - (rgb >> 2); [youtube](https://www.youtube.com)
    
    // 2. DPCM prediction (left/above neighbors)
    int16_t pred_y = prev_y + left_y >> 1;
    int16_t res_y  = y - pred_y;
    
    // 3. Quantize + Huffman code
    uint8_t quant_y = res_y >> qp;
    huffman_encode(quant_y, compressed++);
    
    // 4. Repeat for Co/Cg, rate control
}

Conceptually, DSC shrinks raw pixel streams by predicting/chroma-subsampling within DisplayPort main stream attributes (MSA), enabling 4K@240Hz over DVI-era cables—slice headers negotiate compression ratio during link training alongside CTLE equalization. Decoder mirrors process instantly; gaming monitors auto-enable for VRR compatibility, stress-tested via PRBS patterns ensuring LFSR-generated video maintains 1e-12 BER through compressed pipeline.

/ˌdiː viː ˈaɪ/

n. "Digital video interface transmitting uncompressed TMDS pixel streams as DisplayPort's analog predecessor."

DVI, short for Digital Visual Interface, delivers uncompressed digital video via TMDS (Transition-Minimized Differential Signaling) over 1-2 data pairs (Single-Link=3.96Gbps, Dual-Link=7.92Gbps), supporting 1920x1200@60Hz single/2560x1600@60Hz dual without audio or daisy-chaining unlike modern DisplayPort. Developed by DDWG in 1999 as VGA successor, DVI-D (digital-only), DVI-I (integrated analog/digital), and DVI-A variants bridge CRT-to-LCD transition via 24-pin connectors with optional 5-pin VGA breakout.

Key characteristics of DVI include: TMDS Encoding transitions 8b→10b symbols minimizing EMI (max 165MHz pixel clock single-link); Single/Dual-Link versions double bandwidth via second TMDS pair for QXGA+ resolutions; DVI-D/DVI-I/DVI-A connector variants with 18/24 digital + 0/4/5 analog pins; No Audio/EDID2/hot-plug limitations vs HDMI/DP packetized protocols; Screw-lock mounting ensures desktop stability absent in USB-C ecosystems.

Conceptual example of DVI usage:

-- DVI TMDS encoder behavioral model (10-bit symbol generation)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tmds_encoder is
  port (
    clk   : in  std_logic;
    din   : in  std_logic_vector(7 downto 0);  -- 8-bit pixel data
    dout  : out std_logic_vector(9 downto 0)   -- 10-bit TMDS symbol
  );
end entity;

architecture behavioral of tmds_encoder is
  function count_ones(d : std_logic_vector) return integer is
  begin
    return count_ones(to_integer(unsigned(d)));
  end function;
  
begin
  process(clk)
    variable ones : integer;
  begin
    if rising_edge(clk) then
      ones := count_ones(din);
      if ones > 4 or (ones = 4 and din(7) = '1') then
        dout <= std_logic_vector(to_unsigned(ones*2 - 10, 10));  -- XOR invert
      else
        dout <= std_logic_vector(to_unsigned(10 - ones*2, 10)); -- No invert
      end if;
    end if;
  end process;
end architecture;

Conceptually, DVI blasts raw pixel clock+data through TMDS pairs with fixed 0.5UI eye openings, requiring clean 24AWG cables under 5m unlike USB4 retimers—link training absent forces graphics cards to guess voltage swing unlike DisplayPort LTK. Stress-tested via PRBS generators hitting TMDS receivers with CTLE compensation, now legacy in HDMI/DP era but immortalized in workstation GPUs tunneling through active adapters to 4K@30Hz max.

/ˈdɪspleɪ pɔːrt/

n. "VESA's royalty-free digital audio/video interface transmitting uncompressed pixel streams over HBR/UHBR lanes."

DisplayPort, short for DisplayPort, delivers high-bandwidth digital video/audio via 1-4 differential pairs (HBR3=32.4Gbps, UHBR20=80Gbps), supporting daisy-chaining, Multi-Stream Transport (MST) for 4x 1080p monitors, and Adaptive Sync (FreeSync). Tunnels through USB4 and competes with HDMI via 128b/132b encoding (DP2.1), enabling 16K@60Hz or 8K@240Hz with DSC compression—uses micro-packet architecture with link training unlike DVI's TMDS.

Key characteristics of DisplayPort include: Micro-Packet Architecture transmits blanking/aux data separately from pixels (HBR3=8.1Gbps/lane x4); UHBR Tiers scale from 10/13.5/20Gbps per lane (DP2.1=77.37Gbps payload); Multi-Stream Transport fans out single cable to 3+ displays via time-division multiplexing; Adaptive-Sync eliminates tearing (FreeSync/G-Sync compatible); Daisy-Chaining connects 6+ monitors without hub using DP-in/DP-out ports.

Conceptual example of DisplayPort usage:

/* DP 2.1 Link Training - UHBR20 negotiation */
struct dp_link_training {
    uint8_t voltage_swing;      // 0-3 (400-1200mV)
    uint8_t pre_emphasis;       // 0-3 (0-3.5dB)
    uint8_t post_cursor;        // DFE taps
    bool uhbr20_trained;        // 20Gbps/lane success
};

void dp_lt_train(struct dp_link_training *lt) {
    // Training Pattern 1: Swing/emphasis sweep
    for (lt->voltage_swing = 0; swing < 4; swing++) {
        send_tp1_pattern();
        if (rx_eq_satisfied()) break;
    }
    // TP2: Channel equalization with DFE
    send_tp2_pattern();
    lt->uhbr20_trained = check_ber_lt_1e-8();
    
    // Final: Main stream attributes (MSA)
    set_msa(3840, 2160, 60, 8);  // 4K@60 8bpc
}

Conceptually, DisplayPort streams raw RGB pixels + audio + sideband messages over HBR/UHBR lanes with link training optimizing CTLE/DFE taps per cable length—MST branches one PHY to office monitor daisy-chain while USB4 tunnels DP1.4 inside 40Gbps pipe for laptop docking. Stress-tested via PRBS/LFSR generators hitting 1e-12 BER, with DP80 cables mandatory for UHBR20 unlike HDMI's license walls.

/ˌjuː ɛs biː ˈfɔːr/

n. "Thunderbolt-derived USB-C protocol delivering 40-80Gbps tunneling for data/display/PCIe over single cable."

USB4, short for Universal Serial Bus 4, builds on Intel's Thunderbolt™ 3/4 protocol to deliver 20/40/80Gbps bidirectional bandwidth via USB-C connectors, dynamically tunneling PCIe, DisplayPort 2.1, and USB 3.2 protocols over shared 2-lane links with PAM3 encoding (v2.0). Unlike USB 3.2's fixed SuperSpeed pairs, USB4 Connection Manager allocates 90% link capacity across protocol adapters (2/3 USB3.x isochronous, 1/3 PCIe by default), supporting asymmetric 120Tx/40Rx Gbps and backward compatibility down to USB 2.0 via ALTs (Alternate Modes).

Key characteristics of USB4 include: Asymmetric Bandwidth up to 120Gbps one-way (v2.0 PAM3 over 80G active cables); Protocol Tunneling encapsulates PCIe 4.0 x4, DP 2.1 UHBR20 (80Gbps video), USB3 20Gbps simultaneously; Lane Bonding 2x 20Gbps lanes scale to 40Gbps base (80Gbps v2); USB-C Native requires Type-C connector/cable ecosystem with 240W PD 3.1; Backward Compatibility negotiates USB 3.2/2.0/Thunderbolt 3 via link training.

Conceptual example of USB4 usage:

/* USB4 host controller bandwidth allocation */
struct usb4_cm_bw_alloc {
    uint32_t total_bw_gbps;     // 40/80Gbps post-LT
    uint32_t usb3_bw;           // 2/3 isochronous (24Gbps @40G)
    uint32_t pcie_bw;           // 1/3 PCIe (16Gbps @40G)
    uint32_t dp_bw;             // Tunnel allocation UHBR13.5=40Gbps
};

void usb4_tunnel_dp(int res_x, int res_y, int refresh) {
    // Graphics driver requests DP tunnel BW via SBU signaling
    struct dp_config cfg = {res_x, res_y, refresh, 30};  // bpp
    uint32_t req_bw = calc_dp_bw(&cfg);  // ~54Gbps 4K@144Hz
    usb4_cm_request_tunnel(DP_PROTOCOL, req_bw);
    // CM polls DP IN/OUT adapters, releases excess BW back to pool
}

Conceptually, USB4 transforms USB-C into universal docking cable—simultaneously streaming 4K@144Hz from DisplayPort tunnel, NVMe RAID over PCIe tunnel (3GB/s), and 10Gbps peripherals via USB3 tunnel, with Connection Manager dynamically rebalancing as devices hot-plug. Stress-tested via PRBS/LFSR patterns through CTLE-equipped PHYs; v2.0 PAM3 enables 80Gbps passive 40Gbps cables while active 80G cables hit 120Gbps asymmetric for eGPU/video wall use cases previously requiring Thunderbolt enclosures.

/ˌpiː-siː-ˈaɪ/

n. “The standard expansion bus that connected peripherals before PCIe.”

PCI, short for Peripheral Component Interconnect, is a local computer bus standard introduced in the early 1990s that allowed expansion cards, such as network adapters, sound cards, and graphics cards, to connect directly to a computer’s motherboard. It provided a shared parallel interface for data transfer between the CPU and peripheral devices.

Key characteristics of PCI include:

• Parallel Bus: Uses multiple data lines to transmit several bits simultaneously.
• Bus Mastering: Devices could take control of the bus to transfer data independently of the CPU.
• Shared Bandwidth: All devices on the same PCI bus share total bus bandwidth, potentially limiting speed as more devices are added.
• Plug and Play: Supported automatic device configuration, reducing manual setup.
• Legacy Standard: Mostly replaced by PCIe for higher-speed, point-to-point connections.

Conceptual example of PCI usage:

# Installing a PCI network card in a 1998 desktop
Motherboard has multiple PCI slots
Card communicates with CPU via shared PCI bus
Bandwidth shared with any other PCI devices installed

Conceptually, PCI is like a shared roadway: multiple cars (devices) travel together on the same lanes, which works well for moderate traffic but can become congested with more cars.

In essence, PCI was a foundational standard for connecting peripheral devices to PCs, enabling expansion and modularity before the era of high-speed, dedicated links like PCIe.

/ˌeɪ-dʒiː-ˈpiː/

n. “The dedicated graphics highway of early PCs.”

AGP, short for Accelerated Graphics Port, is a high-speed point-to-point channel introduced in 1997 for connecting graphics cards to a computer’s motherboard. It was designed specifically to improve the performance of 3D graphics by providing a direct pathway between the GPU and system memory, bypassing the slower shared PCI bus.

Key characteristics of AGP include:

• Dedicated Graphics Channel: Ensures the GPU has a direct, high-speed connection to system memory.
• Multiple Data Rates: Versions include 1x, 2x, 4x, and 8x, with higher multipliers increasing throughput.
• Texture Memory Access: Allows the graphics card to fetch textures directly from system RAM, improving 3D rendering performance.
• Point-to-Point: Unlike PCI, which is a shared bus, AGP provides a dedicated link for graphics data.
• Legacy Technology: Replaced by PCI Express (PCIe) starting in the mid-2000s.

Conceptual example of AGP usage:

# Installing a 3D graphics card in a 2002 desktop
Desktop motherboard has AGP 4x slot
GPU fetches textures directly from system RAM via AGP
3D rendering performance improved over PCI

Conceptually, AGP is like giving your graphics card its own dedicated highway to memory instead of sharing a congested main road with other devices.

In essence, AGP was a pivotal step in 3D graphics acceleration, providing higher bandwidth and better performance than PCI, until it was superseded by the more flexible and faster PCIe standard.

/ˌpiː-siː-aɪ-iː/

n. “The high-speed lane that connects your computer’s components.”

PCIe, short for Peripheral Component Interconnect Express, is a high-speed interface standard used to connect expansion cards (such as graphics cards, NVMe SSDs, network cards) directly to a computer’s motherboard. It replaced older PCI and AGP standards by providing faster data transfer rates, lower latency, and scalable lanes for bandwidth-intensive components.

Key characteristics of PCIe include:

• Serial Communication: Uses point-to-point serial lanes rather than shared parallel buses, improving speed and reliability.
• Lane Scalability: Configurations like x1, x4, x8, x16 determine how many lanes are used, affecting bandwidth.
• High Bandwidth: PCIe 4.0 and 5.0 offer multiple gigabytes per second per lane, supporting modern GPUs and NVMe storage.
• Low Latency: Efficient protocol with minimal overhead, ideal for high-performance applications.
• Backward Compatible: PCIe slots support older devices, though speed is limited to the lowest common generation.

Conceptual example of PCIe usage:

# Installing an NVMe SSD
Motherboard has an M.2 PCIe slot
SSD communicates directly with CPU via PCIe lanes
High-speed read/write operations possible without SATA bottleneck

Conceptually, PCIe is like adding express highways between your computer’s critical components — more lanes equal faster, smoother traffic for data.

In essence, PCIe is the modern standard for high-speed expansion and interconnection in computers, enabling fast communication for GPUs, SSDs, network adapters, and other performance-sensitive devices.