/ˈsiː tiː ɛl iː/
n. "Continuous-Time Linear Equalizer circuit compensating high-speed serial link attenuation."
CTLE, short for Continuous-Time Linear Equalizer, is an analog signal processing circuit embedded in high-speed SerDes receivers (PCIe, USB4, 100G Ethernet) that boosts high-frequency components attenuated by copper channel loss, restoring sharp eye diagrams without discrete-time decision feedback complexity. Unlike DFE's nonlinear taps, CTLE applies continuous-time zero peaking at Nyquist/2 frequency via passive R/C ladders or active Gm-C/OTAs, providing linear phase response and low power (~1mW/Gbps) for 56G PAM4/SerDes.
Key characteristics of CTLE include: High-Frequency Boost creates zero in transfer function (DC gain 0dB, peaking 6-15dB at 20GHz+); Passive/Active Topologies with R-C ladders (simple, fixed) vs transconductance amps (adaptive gain); Low Latency continuous-time operation vs FFE/DFE clocked slicing; Multi-Peak/Stripped designs targeting fundamental+harmonics for PAM4 (3dB/octave loss slope compensation).
Conceptual example of CTLE usage:
// Verilog-A behavioral model of 3-tap CTLE
module ctle(dout, din);
electrical din, dout;
parameter real dc_gain = 1.0;
parameter real peaking = 10.0; // dB boost
parameter real freq_3db = 1e9; // Hz
analog begin
V(dout) <+ dc_gain * laplace_nd(1 / (1 + s/(2*`M_PI*freq_3db))) * V(din);
end
endmodule
// SPICE schematic equivalent
R1 din n1 50 // 50-ohm input
C1 n1 n2 100f // High-freq path
R2 n2 dout 300
R3 din dout 50 // Low-freq path (0dB)
Conceptually, CTLE acts like an analog inverse channel filter continuously amplifying faded high frequencies lost in PCB traces/backplanes—deployed first in receiver chain before AGC/DFE, with adaptive variants sampling loss via training sequences. Pairs with FFE for pre-emphasis and DFE for post-cursor ISI in 112G long-reach links, where fixed/peaking knobs tune 10-30dB total equalization for error-free 1e-6 BER at 56Gbaud.