DQS

/ˌdiː kjuː ˈɛs/

n. "DDR memory strobe signal capturing DQ data on both clock edges via source-synchronous timing unlike common system CLK."

DQS, short for Data Strobe, transmits alongside bidirectional DQ pins in DDR4/5 SDRAM—memory controller drives DQS center-aligned during WRITEs (90° phase shift) while DRAM outputs edge-aligned during READs, enabling source-synchronous capture immune to board skew. DLL/PLL centers DQS within DQ eye ensuring setup/hold at 3200MT/s; contrasts system CLK by activating only during burst transfers with preamble Hi-Z→low transition signaling data valid window.

## Key Characteristics - Bidirectional Burst Clock: DQS toggles with DQ transfers only; x8 uses 1 DQS, x16 uses 2 per byte lane. - Phase Alignment: WRITE center-sampled (tDQSS); READ edge-sampled after 90° DLL shift maximizing margins. - Differential Pair: /DQS improves noise rejection vs single-ended; Write Leveling calibrates tDQSQ skew during training. - Preamble/Postamble: Hi-Z→low→Hi-Z brackets 8n burst; ODT terminates during READs preventing reflections. - Gate Training: DQS gating masks invalid edges; per-bit deskew compensates intra-byte skew up to 0.2UI.

// DDR4 controller WRITE timing: DQS center-aligned to DQ
// tCK=0.625ns @3200MT/s, burst BL8=16ns

typedef struct {
    uint8_t dq;  // Byte lane data
    uint8_t dm;     // Data mask
} ddr_burst_t;

void ddr_write(uint32_t addr, ddr_burst_t* burst) {
    // tRCD + tCL latency
    mrr_write_leveling();     // Align DQS to CK
    mrr_vref_dq(0.55);        // Set DQ ODT
    
    // Command phase: ACTIVATE → CAS WRITE
    ddr_cmd(CMD_WRITE, addr);
    
    // tWPRE=1tCK preamble
    dqs_preamble_low();       // Hi-Z → low
    for(int i = 0; i < 8; i++) {  // BL8
        dq_drive(burst->dq[i]);
        dqs_toggle();         // Center DQ window
    }
    dqs_postamble();          // low → Hi-Z
}

Conceptually, DQS solves DDR's half-duplex dilemma—DRAM sources DQS+ DQ during READ (edge-aligned for controller DDIO), controller reverses roles during WRITE (center-aligned via Write Leveling) ensuring fly-by topology timing closure without per-DQ PLLs. ZQ calibration trims RON/RTT matching ODT to 240Ω while PRBS31 stresses RTL flops; integrates with SerDes fabric dumping 64GB/s to HBM over PAM4 links backhauling Bluetooth sensor fusion.