/viː ˈrɛf/
n. — "Voltage midpoint for clean DDR data eyes."
VREF (Voltage REFe rence) generates precise 0.5×VDD midpoint (0.75V for DDR4, 0.55V for DDR5) used by receivers to slice high-speed data signals, originally external resistors/MDACs but internalized per-DIMM in DDR4+, per-lane in GDDR6X PAM4. Receivers compare incoming DQ/DQS against VREF to resolve 0→1 transitions, critical for eye diagram centering as signaling rates climb beyond 3200MT/s where noise margins vanish.
Key characteristics and concepts include:
- Per-DIMM generators in DDR4+, per-lane training in PAM4 GDDR—no more shared global VREF causing rank imbalance.
- Dynamic calibration during initialization, tracking VDD/SSI variations so data slicers stay centered despite droop/overshoot.
- DDR5 internalizes per-subchannel VREF generators, mocking DDR3's fragile global reference daisy chains.
- PAM4 needs multiple VREF slicers (33%/66%) per lane, turning signal integrity into calibration nightmare fuel.
In DDR5 training, controller sweeps VREF DACs per rank/channel while sending PRBS patterns, locking optimal slice points—live operation tracks drift via periodic retraining.
An intuition anchor is to picture VREF as the referee's centerline: data signals oscillate around it, receiver samples exactly at midpoint—drift too far either way and 1s read as 0s despite perfect edges.