CK

/siːˈkeɪ/

n. "Differential DDR clock pair CK/CK# synchronizing command/address at every rising edge unlike source-synchronous DQS."

CK, short for Clock, drives DDR4/5 SDRAM command/address buses on rising edges while /CK# complements provide true differential timing reference—memory DLL aligns internal clocks to CK period (tCK=0.625ns@3200MT/s) ensuring commands sample precisely at 50% duty cycle cross-point. Contrasts per-byte DQS by spanning entire rank with fly-by topology where ODT stubs minimize reflections; Write Leveling aligns DQS-to-CK during training.

## Key Characteristics - Differential Pair CK/CK# rejects noise, centers sampling at 50% voltage cross-point. - Command Clock rising edges register ACT/READ/WRITE; tCK defines interface rate. - Fly-by Topology single CK traces all chips with per-DIMM ODT stubs ≤1" length. - DLL Alignment internal DRAM clocks phase-locked to CK ±50ps jitter budget. - Half-Frequency internal core runs tCK/2 while IO toggles full-rate DDR.

// DDR4 CK generator + command timing
// 3200MT/s = 1600MHz differential CK

module ddr_ck_gen (
    input  clk_ref_800mhz,  // PLL reference  
    input  rst_n,
    output ck_p, ck_n,
    output ddr_clk_1600mhz
);
    reg ck_ff;
    
    // 800MHz → 1600MHz DDR via DDR output flop
    always @(posedge clk_ref_800mhz) 
        ck_ff <= ~ck_ff;
    
    ODDR #(
        .DDR_CLK_EDGE("SAME_EDGE"),
        .INIT(1'b0),
        .SRTYPE("SYNC")
    ) ck_oddr (
        .Q1(ck_p),
        .Q2(ck_n),
        .C0(clk_ref_800mhz),
        .C1(),
        .CE(1'b1),
        .D1(ck_ff),
        .D2(~ck_ff),
        .R(~rst_n),
        .S(1'b0)
    );
    
    assign ddr_clk_1600mhz = clk_ref_800mhz;
    
    // Command timing example
    reg [2:0] cmd;  // RAS/CAS/WE
    always @(posedge ddr_clk_1600mhz) begin
        case (state)
            ACTIVATE: cmd <= 3'b011;
            READ:     cmd <= 3'b101;
            WRITE:    cmd <= 3'b101;
        endcase
    end
endmodule

Conceptually, CK establishes DDR timing backbone—commands pipeline on rising edges while DQS bursts data source-synchronously; Read Capture aligns controller DDIO to returning DQS edges delayed by tDQSCK. Gate training masks invalid DQS while ZQ trims ODT; integrates with SerDes dumping 128GB/s DDR5 to HBM3 over PAM4 feeding Bluetooth edge clusters.