Encoding

/siːˈkeɪ/

n. "Differential DDR clock pair CK/CK# synchronizing command/address at every rising edge unlike source-synchronous DQS."

CK, short for Clock, drives DDR4/5 SDRAM command/address buses on rising edges while /CK# complements provide true differential timing reference—memory DLL aligns internal clocks to CK period (tCK=0.625ns@3200MT/s) ensuring commands sample precisely at 50% duty cycle cross-point. Contrasts per-byte DQS by spanning entire rank with fly-by topology where ODT stubs minimize reflections; Write Leveling aligns DQS-to-CK during training.

## Key Characteristics - Differential Pair CK/CK# rejects noise, centers sampling at 50% voltage cross-point. - Command Clock rising edges register ACT/READ/WRITE; tCK defines interface rate. - Fly-by Topology single CK traces all chips with per-DIMM ODT stubs ≤1" length. - DLL Alignment internal DRAM clocks phase-locked to CK ±50ps jitter budget. - Half-Frequency internal core runs tCK/2 while IO toggles full-rate DDR.

// DDR4 CK generator + command timing
// 3200MT/s = 1600MHz differential CK

module ddr_ck_gen (
    input  clk_ref_800mhz,  // PLL reference  
    input  rst_n,
    output ck_p, ck_n,
    output ddr_clk_1600mhz
);
    reg ck_ff;
    
    // 800MHz → 1600MHz DDR via DDR output flop
    always @(posedge clk_ref_800mhz) 
        ck_ff <= ~ck_ff;
    
    ODDR #(
        .DDR_CLK_EDGE("SAME_EDGE"),
        .INIT(1'b0),
        .SRTYPE("SYNC")
    ) ck_oddr (
        .Q1(ck_p),
        .Q2(ck_n),
        .C0(clk_ref_800mhz),
        .C1(),
        .CE(1'b1),
        .D1(ck_ff),
        .D2(~ck_ff),
        .R(~rst_n),
        .S(1'b0)
    );
    
    assign ddr_clk_1600mhz = clk_ref_800mhz;
    
    // Command timing example
    reg [2:0] cmd;  // RAS/CAS/WE
    always @(posedge ddr_clk_1600mhz) begin
        case (state)
            ACTIVATE: cmd <= 3'b011;
            READ:     cmd <= 3'b101;
            WRITE:    cmd <= 3'b101;
        endcase
    end
endmodule

Conceptually, CK establishes DDR timing backbone—commands pipeline on rising edges while DQS bursts data source-synchronously; Read Capture aligns controller DDIO to returning DQS edges delayed by tDQSCK. Gate training masks invalid DQS while ZQ trims ODT; integrates with SerDes dumping 128GB/s DDR5 to HBM3 over PAM4 feeding Bluetooth edge clusters.

/ˌdiː kjuː ˈɛs/

n. "DDR memory strobe signal capturing DQ data on both clock edges via source-synchronous timing unlike common system CLK."

DQS, short for Data Strobe, transmits alongside bidirectional DQ pins in DDR4/5 SDRAM—memory controller drives DQS center-aligned during WRITEs (90° phase shift) while DRAM outputs edge-aligned during READs, enabling source-synchronous capture immune to board skew. DLL/PLL centers DQS within DQ eye ensuring setup/hold at 3200MT/s; contrasts system CLK by activating only during burst transfers with preamble Hi-Z→low transition signaling data valid window.

## Key Characteristics - Bidirectional Burst Clock: DQS toggles with DQ transfers only; x8 uses 1 DQS, x16 uses 2 per byte lane. - Phase Alignment: WRITE center-sampled (tDQSS); READ edge-sampled after 90° DLL shift maximizing margins. - Differential Pair: /DQS improves noise rejection vs single-ended; Write Leveling calibrates tDQSQ skew during training. - Preamble/Postamble: Hi-Z→low→Hi-Z brackets 8n burst; ODT terminates during READs preventing reflections. - Gate Training: DQS gating masks invalid edges; per-bit deskew compensates intra-byte skew up to 0.2UI.

// DDR4 controller WRITE timing: DQS center-aligned to DQ
// tCK=0.625ns @3200MT/s, burst BL8=16ns

typedef struct {
    uint8_t dq;  // Byte lane data
    uint8_t dm;     // Data mask
} ddr_burst_t;

void ddr_write(uint32_t addr, ddr_burst_t* burst) {
    // tRCD + tCL latency
    mrr_write_leveling();     // Align DQS to CK
    mrr_vref_dq(0.55);        // Set DQ ODT
    
    // Command phase: ACTIVATE → CAS WRITE
    ddr_cmd(CMD_WRITE, addr);
    
    // tWPRE=1tCK preamble
    dqs_preamble_low();       // Hi-Z → low
    for(int i = 0; i < 8; i++) {  // BL8
        dq_drive(burst->dq[i]);
        dqs_toggle();         // Center DQ window
    }
    dqs_postamble();          // low → Hi-Z
}

Conceptually, DQS solves DDR's half-duplex dilemma—DRAM sources DQS+ DQ during READ (edge-aligned for controller DDIO), controller reverses roles during WRITE (center-aligned via Write Leveling) ensuring fly-by topology timing closure without per-DQ PLLs. ZQ calibration trims RON/RTT matching ODT to 240Ω while PRBS31 stresses RTL flops; integrates with SerDes fabric dumping 64GB/s to HBM over PAM4 links backhauling Bluetooth sensor fusion.

/ˌpiː eɪ ɛm ˈfɔːr/

n. "Four-level pulse amplitude modulation encoding two bits per symbol via voltage levels unlike binary NRZ."

PAM4, short for Pulse Amplitude Modulation 4-level, transmits 56Gbps+ over single lanes by mapping 00/01/10/11 to four distinct voltages—SerDes DSP applies FFE/CTLE/DFE to open three squeezed eyes while FEC corrects 1e-6 BER. Contrasts NRZ's two levels by halving baud rate for same throughput but shrinking margins 3x requiring precise ISI equalization.

Key characteristics of PAM4 include: Four Voltage Levels 00=-3/01=-1/10=+1/11=+3 units; Three Eyes stacked with 1/3 NRZ height each; 2b/symbol doubles NRZ capacity at same baud; DSP Intensive FFE+CTLE+DFE+FEC mandatory; Gray Coding adjacent levels differ by 1 bit minimizing errors.

Conceptual example of PAM4 usage:

module pam4_serdes_tx (
    input clk_56g, 
    input [1:0] data_in,  // 2 bits/symbol
    output pam4_p, pam4_n
);
    reg [1:0] gray_code;
    reg [11:0] dac_levels = '{12'd0, 12'd850, 12'd1700, 12'd2550};  // 00/01/10/11
    
    // Gray coding: 00→00, 01→01, 11→11, 10→10
    always @(*) case(data_in)
        2'b00: gray_code = 2'b00;
        2'b01: gray_code = 2'b01;
        2'b11: gray_code = 2'b11;
        2'b10: gray_code = 2'b10;
    endcase
    
    // 12-bit DAC output stage
    wire [11:0] pam4_level = dac_levels[gray_code];
    
    // FFE pre-emphasis tap weights
    wire [11:0] ffe_out = pam4_level + pre_tap1*c1 + post_tap1*c2;
    
    assign pam4_p =  ffe_out;
    assign pam4_n = ~ffe_out;
    
    // PRBS31 generator stresses PAM4 eyes
    reg [30:0] lfsr;
    assign data_in = lfsr ^ lfsr ? 2'b11 : 2'b00;  // Worst-case patterns
    
endmodule

Conceptually, PAM4 stacks three NRZ eyes vertically—SerDes MLSE/DFE slicers resolve ambiguous middle levels while PRBS31 patterns validate bathtub curves for 400G DR8 links backhauling Bluetooth 200Gbps FHSS aggregators. Enables 1.6T spine fabrics where NRZ hits physics wall; contrasts GFSK constant envelope by demanding linear TX/RX amid VHDL-synthesized 224G optics.

/ˌɛn ɑːr ˈziː/

n. "Binary line code maintaining constant voltage levels for each bit without returning to zero between symbols unlike RZ."

NRZ, short for Non-Return-to-Zero, encodes digital data by holding high voltage for logic 1 and low voltage for logic 0 throughout the entire bit period—SerDes transmitters drive differential pairs at 28Gbps using NRZ before CTLE equalization compensates ISI. Contrasts RZ's mid-bit return-to-zero pulse by eliminating unnecessary transitions that double bandwidth while introducing baseline wander from long runs of identical bits.

Key characteristics of NRZ include: Two-Level Encoding +V/–V represents 1/0 without zero state; No Bit Transitions consecutive 1s/0s stay high/low continuously; DC Wander long runs cause baseline shift requiring DFE adaptation; 1b/s/Hz Spectral Efficiency half transitions vs Manchester; Clock Recovery PLL extracts timing from edge density.

Conceptual example of NRZ usage:

`timescale 1ns/1ps
module nrz_serializer (
  input clk_28g, nrz_data_in, 
  output serdes_tx_p, serdes_tx_n
);

// 64b/66b encoder → NRZ serializer → CML driver
reg [63:0] data_buf;
reg nrz_out;

always @(posedge clk_28g) begin
  // Gray code counter prevents meta-stability
  if (nrz_data_in) nrz_out <= 1'b1;  // Hold HIGH
  else             nrz_out <= 1'b0;  // Hold LOW
end

// Differential CML output stage
assign serdes_tx_p =  nrz_out ? 1'b1 : 1'b0;
assign serdes_tx_n = ~nrz_out ? 1'b1 : 1'b0;

// PRBS7 pattern generator for BIST
reg [6:0] lfsr = 7'h7F;
wire prbs_bit = lfsr ^ lfsr;
always @(posedge clk_28g) lfsr <= {lfsr[5:0], prbs_bit};

endmodule

Conceptually, NRZ maximizes spectral efficiency by eliminating RZ's wasteful mid-bit returns—SerDes CDR recovers clock from statistical transitions while PRBS patterns stress eye diagrams for BIST validation. Long 0/1 runs cause DC wander mitigated by DFE slicer adaptation; contrasts PAM4's 4-level encoding by preserving 25-56Gbps signaling before upgrading to 100G+ PAM4 links in Bluetooth gateways handling FHSS backhaul.