/ˌdiː diː ˈɑːr wʌn/
n. — “DDR1: the plucky SDRAM pioneer that discovered both clock edges work, kickstarting the DDR dynasty before anyone cared.”
DDR1 (Double Data Rate 1) SDRAM introduced dual-edge data transfers at 2.5-2.6V with 2n prefetch architecture, 100-200MHz clocks (200-400MT/s effective), and source-synchronous DQS strobes to double bandwidth over SDR without clock frequency insanity. Building on DRAM leaky cells with four banks and SSTL_2 I/O, DDR1 pipelines activate-CAS bursts through DLL-aligned interfaces while commands single-pump on CK edges, launching PC-2100/PC-2700 DIMMs that fueled early 2000s Pentium 4s before DDR2 voltage diets arrived.
Key characteristics and concepts include:
- 2n prefetch bursting two column words per activate to pins, mocking SDR's single-edge stinginess at the cost of doubled internal pipelining.
- Single DQS strobe per data group (edge-aligned reads, center-aligned writes), pretending global CK distribution doesn't suck at >133MHz.
- Four banks with no bank groups, basic ODT-lite termination, and 2.5V SSTL_2 pretending signal integrity scales beyond two DIMMs/channel.
- CAS 2-3 latencies with burst lengths 2/4/8, auto-precharge options, and 7.8µs refresh intervals mocking async DRAM's timing anarchy.
In a classic Northbridge controller waltz, DDR1 interleaves rank accesses across stubby multi-DIMM channels, chasing row hit bliss while DLLs fight CK-DQS skew—delivering 3.2GB/s dual-channel glory until DDR2's prefetch muscles flexed harder.
An intuition anchor is to picture DDR1 as SDRAM's rebellious teenager: data on *both* clock edges instead of just rising like a prude, birthing modern GDDR mutants while sipping 2.5V like it owned the place.