/diː ˈræm/
n. — “DRAM: the leaky bucket brigade of computing memory, forcing constant refresh orgies to pretend bits don't evaporate.”
DRAM (Dynamic Random Access Memory) stores each bit as charge in a tiny capacitor within a transistor-gated cell array, requiring periodic refresh cycles because leakage turns data into digital amnesia within milliseconds. Organized into a 2D grid of rows and columns addressable via multiplexers, DRAM dumps entire rows into sense amplifiers during activate commands, then services burst read/write from the open page for low-latency hits or precharge to close it. This volatile, dense design underpins SDRAM, SGRAM, and all DDR/GDDR families, mocking SRAM's power-hogging stability.
Key characteristics and concepts include:
- 1T1C cell structure where capacitors charge-share with bitlines during sense amp striping, pretending analog noise doesn't corrupt marginal voltages.
- Rowhammer vulnerability from field-effect leakage between adjacent wordlines, because physics hates free density lunch.
- Burst lengths and CAS latencies tuning throughput vs latency, with page-mode hits tricking CPUs into spatial locality bliss.
- Distributed refresh sweeps (every 64ms) stealing tRFC cycles from user traffic, because leaky caps demand tribute.
In a system bus workflow, DDR controllers hammer DRAM with activate-read storms for cache-line fills, banking on open-page policies to minimize tRCD/tRP penalties while refresh daemons lurk.
An intuition anchor is to picture DRAM as a stadium of water clocks: dense and cheap, but leaky enough to need constant bucket brigades, unlike SRAM's lazy flip-flop loungers sipping zero refresh.