/ˌɛn ɑːr ˈziː/
n. "Binary line code maintaining constant voltage levels for each bit without returning to zero between symbols unlike RZ."
NRZ, short for Non-Return-to-Zero, encodes digital data by holding high voltage for logic 1 and low voltage for logic 0 throughout the entire bit period—SerDes transmitters drive differential pairs at 28Gbps using NRZ before CTLE equalization compensates ISI. Contrasts RZ's mid-bit return-to-zero pulse by eliminating unnecessary transitions that double bandwidth while introducing baseline wander from long runs of identical bits.
Key characteristics of NRZ include: Two-Level Encoding +V/–V represents 1/0 without zero state; No Bit Transitions consecutive 1s/0s stay high/low continuously; DC Wander long runs cause baseline shift requiring DFE adaptation; 1b/s/Hz Spectral Efficiency half transitions vs Manchester; Clock Recovery PLL extracts timing from edge density.
Conceptual example of NRZ usage:
`timescale 1ns/1ps
module nrz_serializer (
input clk_28g, nrz_data_in,
output serdes_tx_p, serdes_tx_n
);
// 64b/66b encoder → NRZ serializer → CML driver
reg [63:0] data_buf;
reg nrz_out;
always @(posedge clk_28g) begin
// Gray code counter prevents meta-stability
if (nrz_data_in) nrz_out <= 1'b1; // Hold HIGH
else nrz_out <= 1'b0; // Hold LOW
end
// Differential CML output stage
assign serdes_tx_p = nrz_out ? 1'b1 : 1'b0;
assign serdes_tx_n = ~nrz_out ? 1'b1 : 1'b0;
// PRBS7 pattern generator for BIST
reg [6:0] lfsr = 7'h7F;
wire prbs_bit = lfsr ^ lfsr;
always @(posedge clk_28g) lfsr <= {lfsr[5:0], prbs_bit};
endmodule
Conceptually, NRZ maximizes spectral efficiency by eliminating RZ's wasteful mid-bit returns—SerDes CDR recovers clock from statistical transitions while PRBS patterns stress eye diagrams for BIST validation. Long 0/1 runs cause DC wander mitigated by DFE slicer adaptation; contrasts PAM4's 4-level encoding by preserving 25-56Gbps signaling before upgrading to 100G+ PAM4 links in Bluetooth gateways handling FHSS backhaul.