/ˌoʊ diː ˈtiː/
n. — "ODT: termination resistors hiding inside DRAM dies, mocking external resistor packs while pretending signal reflections never happened."
ODT (On-Die Termination) integrates switchable termination resistors directly within DRAM and controller I/O to match transmission line impedance, eliminating PCB-mounted resistors and enabling dynamic termination control during DDR read/write/receive operations across multi-drop buses. Configured via mode register bits (Rtt_Nom, Rtt_Wr, Rtt_Park) with values like 120Ω/60Ω/40Ω, ODT turns on precisely when needed—controller during writes, far-end DDR during reads—preventing stubs from ringing like church bells while GDDR controllers juggle per-lane settings for PAM4 madness.
Key characteristics and concepts include:
- Dynamic enable/disable via ODT pins and mode registers, turning termination on just before data windows and off immediately after to save power and eliminate reflections.
- Rtt values (34Ω-120Ω) selected per operation type: nominal for steady-state, write for bidirectional bus turnarounds, park for idle termination across all ranks.
- Multi-rank coordination where non-accessed DDR devices provide parallel termination (Rtt/2 effective), mocking single-drop simplicity.
- PAM4/GDDR6X complexity demanding per-lane ODT calibration because four tiny eyes need surgical signal integrity.
In a dual-rank DDR3 write, controller enables ODT on both ranks (Rtt_Wr=60Ω), far-end rank drives data with its ODT off during turnaround, then both enable Rtt_Nom during controller read—keeping fly-by stubs quiet without external resistor graveyards.
An intuition anchor is to picture ODT as bouncers inside each DRAM chip: they slam the door on reflections exactly when signals arrive, then step aside to let data pass, eliminating the external resistor moats that DDR1 needed just to survive multi-DIMM channels.