/ˌiː siː ˈsiː/
n. — "Extra bits catching flipped data before it corrupts your server."
ECC (Error Correcting Code) memory adds 7-8 parity bits per 64 data bits using Hamming codes to detect/correct single-bit errors and detect multi-bit faults in DRAM, standard for servers/workstations where cosmic rays or voltage noise flip bits during long-running workloads. Unlike consumer DDR, ECC modules use 9 chips (8 data + 1 parity) with controller support for SECDED (single error correction, double error detection), mandatory on-die ECC in DDR5 scrubbing internal cell errors invisible to system.
Key characteristics and concepts include:
- Hamming(72,64) encoding 7 parity bits per 64 data bits, correcting 1-bit flips, detecting 2-bit errors via syndrome decoding.
- Server ECC RDIMMs vs consumer non-parity DIMMs, x9 organization vs x8 with system controller overhead ~1-2% performance.
- On-die ECC in DDR5/LPDDR5X scrubs internal 128b blocks to 120b data, invisible to memory controller.
- Critical for financial/scientific workloads where 1 bit-flip = million-dollar trades or physics discoveries ruined.
In server memory traffic, DDR5 controller writes 64b data + 8b ECC, readback recomputes syndrome—if non-zero, flips corrected bit and logs CE (correctable error), DE halts system.
An intuition anchor is to picture ECC as spellcheck for binary: single typos auto-fixed, double typos flagged for manual review—keeping server ledgers pristine while consumer RAM gambles on cosmic ray roulette.