LFSR

/ˌɛl ɛf ɛs ɑːr/

n. "Shift register circuit generating pseudorandom sequences via linear feedback for PRBS and crypto primitives."

LFSR, short for Linear Feedback Shift Register, comprises n D-flip-flops in series where selected tap bits XOR together to form the input bit, creating maximal-length sequences of 2ⁿ-1 states when using primitive polynomials over GF(2). Powers PRBS generators in SerDes testing, stream ciphers (Bluetooth E0), and BIST—Fibonacci (external XOR) vs Galois (internal XOR) configurations trade area for timing, with non-zero seeds avoiding lockup.

Key characteristics of LFSR include: Maximal Period 2ⁿ-1 states via primitive polynomials (x³¹+x²⁸+1); Linear Feedback XOR of tap bits [n-1, k] defines characteristic polynomial; Balance near 50/50 1s/0s with white-noise autocorrelation; Hardware Efficiency ~n FFs + (t-1) XORs for t taps; Deterministic repeatable from seed unlike true RNGs.

Conceptual example of LFSR usage:

// 4-bit LFSR (x^4 + x^3 + 1) Fibonacci configuration
module lfsr4 (
  input  clk, rst_n, en,
  output reg out_bit
);
  reg [3:0] sreg = 4'b1001;  // Seed != 0000
  
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) 
      sreg <= 4'b1001;
    else if (en) begin
      out_bit <= sreg;
      sreg <= {sreg[2:0], sreg ^ sreg};
    end
  end
endmodule

// Expected sequence: 1001 → 0011 → 1011 → 0110 → 1010 → 0101 → 1000 → 0010 → 0100 → 1000 (repeats)

Conceptually, LFSR functions like a compact pseudorandom number generator where flip-flop chain shifts right while XOR feedback injects next bit—feeding PRBS testers, CTLE stress patterns, and BIST logic. Galois LFSRs parallelize better for high-speed (one XOR per bit), while Fibonacci cascades taps externally; self-test via signature analysis compresses scan chains, making LFSRs ubiquitous in ASIC/FPGA verification alongside zsh scripting and pip simulation environments.