VHDL

/ˌviː eɪtʃ diː ˈɛl/

n. "Ada-derived HDL for modeling RTL behavior and structure in ASICs and FPGAs unlike C++ SystemVerilog."

VHDL, short for VHSIC Hardware Description Language, standardizes digital circuit specification at RTL with entity/architecture paradigm—entity declares ports while architecture describes concurrent behavior using processes, signals, and component instantiations for synthesis to gates or simulation. Developed 1980s by US DoD VHSIC program, VHDL's strongly-typed syntax contrasts Verilog's C-like proceduralism, enabling formal verification and multi-level modeling from behavioral to gate-level for SerDes CTLE controllers and BIST engines.

Key characteristics of VHDL include: Strongly Typed std_logic/std_logic_vector vs Verilog's reg/wire; Entity/Architecture separation declaring blackbox interface + implementation; Concurrent Signal Assignment always active unlike Verilog blocking; Process Sensitivity Lists trigger sequential code on signal edges; Generics/Configurations enable parameterized, multi-architecture designs; Strongly-Typed Enumerations/Records for state machines/self-documenting enums.

Conceptual example of VHDL usage:

-- PRBS-7 generator entity/architecture for SerDes BIST
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity prbs7_gen is
    generic ( SEED : std_logic_vector(6 downto 0) := "1000001" );
    port (
        clk     : in  std_logic;
        rst_n   : in  std_logic;
        enable  : in  std_logic;
        prbs_out: out std_logic
    );
end entity prbs7_gen;

architecture behavioral of prbs7_gen is
    signal lfsr_reg : std_logic_vector(6 downto 0) := SEED;
begin
    process(clk, rst_n)
    begin
        if rst_n = '0' then
            lfsr_reg <= SEED;
        elsif rising_edge(clk) and enable = '1' then
            prbs_out <= lfsr_reg(0);  -- LSB output
            lfsr_reg <= lfsr_reg(5 downto 0) & (lfsr_reg(6) xor lfsr_reg(5));
        end if;
    end process;
end architecture behavioral;

-- Component instantiation in parent module
U_PRBS: prbs7_gen port map (...);

Conceptually, VHDL describes hardware as concurrent entities communicating via signals—processes model sequential logic like LFSR state machines while structural architectures instantiate gates or IPs for SerDes TX/RX paths. Synthesizers infer FFs from clocked processes, muxes from case statements; formal tools verify properties unlike Verilog's race conditions. Powers BIST controllers validating PRBS generators and DFE tap adaptation in production silicon.