DVI

/ˌdiː viː ˈaɪ/

n. "Digital video interface transmitting uncompressed TMDS pixel streams as DisplayPort's analog predecessor."

DVI, short for Digital Visual Interface, delivers uncompressed digital video via TMDS (Transition-Minimized Differential Signaling) over 1-2 data pairs (Single-Link=3.96Gbps, Dual-Link=7.92Gbps), supporting 1920x1200@60Hz single/2560x1600@60Hz dual without audio or daisy-chaining unlike modern DisplayPort. Developed by DDWG in 1999 as VGA successor, DVI-D (digital-only), DVI-I (integrated analog/digital), and DVI-A variants bridge CRT-to-LCD transition via 24-pin connectors with optional 5-pin VGA breakout.

Key characteristics of DVI include: TMDS Encoding transitions 8b→10b symbols minimizing EMI (max 165MHz pixel clock single-link); Single/Dual-Link versions double bandwidth via second TMDS pair for QXGA+ resolutions; DVI-D/DVI-I/DVI-A connector variants with 18/24 digital + 0/4/5 analog pins; No Audio/EDID2/hot-plug limitations vs HDMI/DP packetized protocols; Screw-lock mounting ensures desktop stability absent in USB-C ecosystems.

Conceptual example of DVI usage:

-- DVI TMDS encoder behavioral model (10-bit symbol generation)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tmds_encoder is
  port (
    clk   : in  std_logic;
    din   : in  std_logic_vector(7 downto 0);  -- 8-bit pixel data
    dout  : out std_logic_vector(9 downto 0)   -- 10-bit TMDS symbol
  );
end entity;

architecture behavioral of tmds_encoder is
  function count_ones(d : std_logic_vector) return integer is
  begin
    return count_ones(to_integer(unsigned(d)));
  end function;
  
begin
  process(clk)
    variable ones : integer;
  begin
    if rising_edge(clk) then
      ones := count_ones(din);
      if ones > 4 or (ones = 4 and din(7) = '1') then
        dout <= std_logic_vector(to_unsigned(ones*2 - 10, 10));  -- XOR invert
      else
        dout <= std_logic_vector(to_unsigned(10 - ones*2, 10)); -- No invert
      end if;
    end if;
  end process;
end architecture;

Conceptually, DVI blasts raw pixel clock+data through TMDS pairs with fixed 0.5UI eye openings, requiring clean 24AWG cables under 5m unlike USB4 retimers—link training absent forces graphics cards to guess voltage swing unlike DisplayPort LTK. Stress-tested via PRBS generators hitting TMDS receivers with CTLE compensation, now legacy in HDMI/DP era but immortalized in workstation GPUs tunneling through active adapters to 4K@30Hz max.