/ˌjuː ɛs biː ˈfɔːr/
n. "Thunderbolt-derived USB-C protocol delivering 40-80Gbps tunneling for data/display/PCIe over single cable."
USB4, short for Universal Serial Bus 4, builds on Intel's Thunderbolt™ 3/4 protocol to deliver 20/40/80Gbps bidirectional bandwidth via USB-C connectors, dynamically tunneling PCIe, DisplayPort 2.1, and USB 3.2 protocols over shared 2-lane links with PAM3 encoding (v2.0). Unlike USB 3.2's fixed SuperSpeed pairs, USB4 Connection Manager allocates 90% link capacity across protocol adapters (2/3 USB3.x isochronous, 1/3 PCIe by default), supporting asymmetric 120Tx/40Rx Gbps and backward compatibility down to USB 2.0 via ALTs (Alternate Modes).
Key characteristics of USB4 include: Asymmetric Bandwidth up to 120Gbps one-way (v2.0 PAM3 over 80G active cables); Protocol Tunneling encapsulates PCIe 4.0 x4, DP 2.1 UHBR20 (80Gbps video), USB3 20Gbps simultaneously; Lane Bonding 2x 20Gbps lanes scale to 40Gbps base (80Gbps v2); USB-C Native requires Type-C connector/cable ecosystem with 240W PD 3.1; Backward Compatibility negotiates USB 3.2/2.0/Thunderbolt 3 via link training.
Conceptual example of USB4 usage:
/* USB4 host controller bandwidth allocation */
struct usb4_cm_bw_alloc {
uint32_t total_bw_gbps; // 40/80Gbps post-LT
uint32_t usb3_bw; // 2/3 isochronous (24Gbps @40G)
uint32_t pcie_bw; // 1/3 PCIe (16Gbps @40G)
uint32_t dp_bw; // Tunnel allocation UHBR13.5=40Gbps
};
void usb4_tunnel_dp(int res_x, int res_y, int refresh) {
// Graphics driver requests DP tunnel BW via SBU signaling
struct dp_config cfg = {res_x, res_y, refresh, 30}; // bpp
uint32_t req_bw = calc_dp_bw(&cfg); // ~54Gbps 4K@144Hz
usb4_cm_request_tunnel(DP_PROTOCOL, req_bw);
// CM polls DP IN/OUT adapters, releases excess BW back to pool
}Conceptually, USB4 transforms USB-C into universal docking cable—simultaneously streaming 4K@144Hz from DisplayPort tunnel, NVMe RAID over PCIe tunnel (3GB/s), and 10Gbps peripherals via USB3 tunnel, with Connection Manager dynamically rebalancing as devices hot-plug. Stress-tested via PRBS/LFSR patterns through CTLE-equipped PHYs; v2.0 PAM3 enables 80Gbps passive 40Gbps cables while active 80G cables hit 120Gbps asymmetric for eGPU/video wall use cases previously requiring Thunderbolt enclosures.