/ˌdiː juː ˈtiː/
n. "Electronic component or system currently undergoing validation by BERT or oscilloscope against specifications."
DUT, short for Device Under Test, refers to any hardware (chip, board, cable assembly, or full system) actively probed during characterization, compliance validation, or production testing—connected to test equipment like BERTs, oscilloscopes, or protocol analyzers measuring performance against datasheet guarantees. In SerDes validation, DUT receives stressed PRBS patterns through channel impairments, with RX eye diagrams and BER logged via loopback or golden PLL modes.
Key characteristics of DUT include: Test Fixture Integration via pogo pins/bed-of-nails or SMPM coax for SMA breakouts; Loopback Mode shorts TX→RX internally for self-contained PHY validation; Golden Reference compares against characterized path loss/insertion; Fixture De-embedding removes test board effects from raw S-parameters; Production ATE scales single-DUT probing to 1000s/hour via handler interface.
Conceptual example of DUT usage:
# Python ATE script characterizing SerDes DUT
import pyvisa
import numpy as np
# Connect BERT to DUT SerDes RX via SMA
bert = pyvisa.ResourceManager().open_resource('TCPIP::BERT_IP::INSTR')
scope = pyvisa.ResourceManager().open_resource('TCPIP::SCOPE_IP::INSTR')
# Stress DUT with PRBS31 + 14.1dB loss
bert.write(':CHAN:LOSS 14.1') # Backplane emulation
bert.write(':PAT:TYPE PRBS31') # LFSR pattern
bert.write(':TEST:BITS 1e12') # 1Tbit test time
bert.write(':TEST:START')
# Measure RX eye on scope
scope.write(':MEAS:EYE:HEIGHT?') # 200mV min spec
eye_height = float(scope.query())
scope.write(':MEAS:BER? 1e-6') # Projected BER
print(f"DUT RX eye: {eye_height}mV, BERT: {bert.query(':TEST:BER?')}")
# Pass/fail vs USB4 spec
assert eye_height > 180e-3 and float(bert.query(':TEST:BER?')) < 1e-12Conceptually, DUT transforms from silicon prototype to validated product when stressed by PRBS through CTLE-equipped channels—BERT counts errors while VNA characterizes Sdd21/Sscd21 margins. Production handlers robotically dock 1000s DUT/hour into ATE sockets, where parametric specs (eye=180mV min, BER=1e-12) gate shipments; contrasts SUT (full system) by isolating PHY silicon pre-board spin. Indispensable for USB4, DisplayPort, PCIe Gen6 qualification hitting bathtub Q>15dB margins.