/peɪdʒ/
n. — "Open row's data latched in sense amps, primed for fast CAS column grabs."
Page is the open row state in DRAM after row activation dumps thousands of cells onto sense amplifiers, creating a cache where subsequent CAS commands access columns with minimal latency instead of full row cycles. Row hits keep the page open for rapid sequential CAS bursts, while conflicts force precharge + new activation, crippling throughput as controllers predict spatial locality across DDR banks.
Key characteristics and concepts include:
- One open page per bank: CAS to same page = instant column decode vs full activation+CAS for conflicts.
- Page-mode chaining multiple CAS cycles while row stays active, classic DRAM speed trick.
- Controllers favor open-page policies betting sequential access stays within active page.
- tRAS caps page lifetime before forced precharge, balancing refresh vs retention.
In DDR4 streaming, activate row47 opens page, CAS col3/7/15 grab columns (row hit), precharge closes, activate row128 (row miss)—repeat while banks hide latency by parallel page juggling.
An intuition anchor is to picture DRAM page as a restaurant counter stocked after kitchen opens pantry: CAS grabs specific items instantly while counter stays loaded—closing/re-stocking wastes time servers hate.