Timing

/tiː ɑːr ˈpiː/

n. — "Row close-to-next-open delay—DRAM's precharge housekeeping timer."

tRP (Row Precharge time) measures minimum clock cycles required to complete precharge (PRE) command and prepare a DRAM bank for new row activation, typically 10-18 cycles terminating the open page state before next ACT command. Third timing parameter (CL-tRCD-tRP-tRAS), tRP triggers on row conflicts when controllers swap pages, combining with tRCD for full row-cycle penalty while DDR prefetch masks sequential hits. Scales ~12-15ns across generations despite clock inflation, critical for random access where row thrashing murders bandwidth.

Key characteristics and concepts include:

• Row conflict penalty = tRP + tRCD + CL, versus pure CL for page hits—controllers chase spatial locality to dodge this tax.
• All-bank precharge (PREAB) resets entire chip (tRP × banks), used during refresh or power-down sequences.
• Separate tRP values per bank group in DDR4+ reflecting internal timing variations.
• Stays ~13ns constant (tRP=15×0.867ns @DDR4-3200), mocking MT/s race while dominating random-access benchmarks.

In DDR5 random stream, PRE row47 closes page (tRP=36 cycles=12ns), ACT row128 (tRCD=36), CAS col3 (CL=36)—full 84-cycle row miss vs 36-cycle page hit, repeat across 32 banks while scheduler hunts locality.

An intuition anchor is to picture tRP as kitchen cleanup after serving from stocked counter: PRE command wipes surfaces (sense amps discharge), tRP waits for dry before restocking—rushed cleanup leaves residue, slow cleanup idles hungry customers.

/tiː ɑːr siː ˈdiː/

n. — "Row activation to CAS delay—DRAM's 'kitchen ready' timer."

tRCD (Row address to Column address Delay) measures minimum clock cycles between row activation (ACT) and CAS read/write command in DRAM, typically 10-18 cycles where sense amplifiers stabilize the open page before column access. Listed as second timing parameter (CL-tRCD-tRP-tRAS), tRCD governs random access latency (=tRCD+CL) while DDR prefetch hides sequential sins, scaling roughly constant ~13-15ns across generations despite clock inflation.

Key characteristics and concepts include:

• Critical path for row miss → first data: ACT waits tRCD, then CAS waits CL—total random latency benchmark.
• Separate read/write values (tRCDRD/tRCDWR) in DDR4+ reflecting DQS strobe vs command timing differences.
• Bank interleaving hides one tRCD while others process, essential for GDDR shader streams.
• True latency (ns) = cycles × (2000/MT/s), staying ~12-15ns from DDR1 (tRCD=2×500ns) to DDR5 (tRCD=36×0.357ns).

In DDR5 random access, ACT row47 (tRCD=36 cycles=12ns), CAS col3 (CL=36=12ns), data via DQS—repeat across 32 banks while controller chases row hits to dodge full tRCD+CL penalty.

An intuition anchor is to picture tRCD as kitchen prep after ordering: row activation stocks counters (sense amps stable), tRCD waits for organization before waiter (CAS) grabs your plate—rushed prep burns food, idle prep wastes time.

/peɪdʒ/

n. — "Open row's data latched in sense amps, primed for fast CAS column grabs."

Page is the open row state in DRAM after row activation dumps thousands of cells onto sense amplifiers, creating a cache where subsequent CAS commands access columns with minimal latency instead of full row cycles. Row hits keep the page open for rapid sequential CAS bursts, while conflicts force precharge + new activation, crippling throughput as controllers predict spatial locality across DDR banks.

Key characteristics and concepts include:

• One open page per bank: CAS to same page = instant column decode vs full activation+CAS for conflicts.
• Page-mode chaining multiple CAS cycles while row stays active, classic DRAM speed trick.
• Controllers favor open-page policies betting sequential access stays within active page.
• tRAS caps page lifetime before forced precharge, balancing refresh vs retention.

In DDR4 streaming, activate row47 opens page, CAS col3/7/15 grab columns (row hit), precharge closes, activate row128 (row miss)—repeat while banks hide latency by parallel page juggling.

An intuition anchor is to picture DRAM page as a restaurant counter stocked after kitchen opens pantry: CAS grabs specific items instantly while counter stays loaded—closing/re-stocking wastes time servers hate.

/roʊ/

n. — "DRAM's horizontal data platter that must activate before CAS can serve column snacks."

Row activation (ACT command) in DRAM dumps an entire row's worth of capacitors (~1K-16K cells) onto sense amplifiers via wordline assertion, opening the page for subsequent CAS column reads/writes measured by tRCD latency (row-to-column delay). Measured in clock cycles (tRCD=10-18), row hits skip re-activation for instant CAS while conflicts force tRP precharge + new ACT, crippling bandwidth as controllers chase spatial locality across DDR banks.

Key characteristics and concepts include:

• Wordline assertion connects entire row (~8KB) to bitlines, sense amps latch charge differences—tRCD waits for stable voltages before CAS releases column data.
• Row hit policy keeps hot rows open for back-to-back CAS, row conflict closes (tRP) then reopens (tRCD+CAS)—classic latency vs throughput war.
• Bank-level parallelism hides one row cycle while others cook, critical for GDDR shader traffic pretending random access exists.
• tRAS (row active time) caps how long a row lingers before forced precharge, balancing refresh needs against greedy open-page policies.

In a DDR4 stream, ACT row0 (tRCD=13), CAS col47 (CL=16), CAS col128 (row hit), PRE row0 (tRP=13), ACT row42 (tRCD), CAS col3—repeat across 16 banks while controller predicts the next winning row.

An intuition anchor is to picture DRAM row as a restaurant kitchen: ACT swings open the pantry door dumping ingredients onto counters (sense amps), CAS grabs specific shelves—leaving the pantry open risks spoilage (tRAS), closing/reopening wastes time (row conflict).