PRBS

/piː ɑːr biː ɛs/

n. "Deterministic bitstream mimicking true randomness via linear feedback shift registers for high-speed link stress testing."

PRBS, short for Pseudorandom Binary Sequence, generates repeatable "random" binary patterns using LFSR polynomials that cycle through 2ⁿ-1 states (PRBS7=127 bits, PRBS31=2.1 billion bits), validating SerDes performance in PCIe, USB4, and Ethernet links by measuring bit error rates under worst-case jitter/ISI conditions. Unlike true random sources, PRBS enables precise error injection and pattern matching between transmitter and receiver, with broadband spectral properties stressing CTLE equalizers and CDR phase detectors.

Key characteristics of PRBS include: Maximal Length cycles through 2ⁿ-1 states avoiding pathological all-zero patterns; Primitive Polynomial taps like x⁷+x⁶+1 define sequence generation; Balanced 50/50 duty cycle with delta-function autocorrelation; DC-null spectrum ideal for AC-coupled receivers; Deterministic repeatability enables precise BER measurements down to 1e-15 without long test times.

Conceptual example of PRBS usage:

// PRBS-15 generator (x^15 + x^14 + 1) for 32G SerDes
module prbs15 (
  input  clk, rst_n, enable,
  output reg prbs_out
);
  reg [14:0] lfsr = 15'h4000;  // Non-zero seed
  
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      lfsr <= 15'h4000;
    end else if (enable) begin
      prbs_out <= lfsr;
      lfsr <= {lfsr[13:0], lfsr ^ lfsr};
    end
  end
endmodule

// SystemVerilog test: verify pattern repetition
`timescale 1ns/1ps
module tb_prbs;
  logic clk = 0, rst_n = 0, en = 0;
  logic out;
  prbs15 dut (.*);
  
  always #5 clk = ~clk;
  initial begin
    #10 rst_n = 1; en = 1;
    #1us $display("PRBS15 lock complete");
  end
endmodule

Conceptually, PRBS functions like a digital stress test pattern that appears random but repeats perfectly, allowing BERT testers and oscilloscopes to validate equalization (CTLE, DFE) and clock recovery across PCB traces and backplanes. PRBS31 stresses 112G PAM4 links while PRBSQ variants test quadrature crosstalk; pattern lock detectors confirm synchronization before BER counters accumulate errors, making it indispensable for validating SerDes IP from concept through production qualification.