/tiː ɑːr ˈpiː/
n. — "Row close-to-next-open delay—DRAM's precharge housekeeping timer."
tRP (Row Precharge time) measures minimum clock cycles required to complete precharge (PRE) command and prepare a DRAM bank for new row activation, typically 10-18 cycles terminating the open page state before next ACT command. Third timing parameter (CL-tRCD-tRP-tRAS), tRP triggers on row conflicts when controllers swap pages, combining with tRCD for full row-cycle penalty while DDR prefetch masks sequential hits. Scales ~12-15ns across generations despite clock inflation, critical for random access where row thrashing murders bandwidth.
Key characteristics and concepts include:
- Row conflict penalty = tRP + tRCD + CL, versus pure CL for page hits—controllers chase spatial locality to dodge this tax.
- All-bank precharge (PREAB) resets entire chip (tRP × banks), used during refresh or power-down sequences.
- Separate tRP values per bank group in DDR4+ reflecting internal timing variations.
- Stays ~13ns constant (tRP=15×0.867ns @DDR4-3200), mocking MT/s race while dominating random-access benchmarks.
In DDR5 random stream, PRE row47 closes page (tRP=36 cycles=12ns), ACT row128 (tRCD=36), CAS col3 (CL=36)—full 84-cycle row miss vs 36-cycle page hit, repeat across 32 banks while scheduler hunts locality.
An intuition anchor is to picture tRP as kitchen cleanup after serving from stocked counter: PRE command wipes surfaces (sense amps discharge), tRP waits for dry before restocking—rushed cleanup leaves residue, slow cleanup idles hungry customers.