BIST

/bɪst/

n. "Self-contained test circuitry embedded within ICs generating PRBS patterns to validate SerDes and logic post-manufacturing."

BIST, short for Built-In Self-Test, integrates pattern generators, response analyzers, and control logic directly into silicon enabling at-speed functional testing without external ATE—crucial for validating SerDes CTLE/DFE convergence, memory arrays, and random logic using LFSR-driven patterns with MISR (Multiple Input Signature Register) compaction. LBIST (Logic BIST) stresses datapaths while MBIST (Memory BIST) marches/march13N patterns through SRAM detecting stuck-at/coupling faults.

Key characteristics of BIST include: On-Chip Pattern Generation via PRPG (LFSR/LFSR+ROM) eliminates external vector loading; Response Compaction condenses millions test bits into 32-512b signature via MISR; At-Speed Testing clocked at mission frequency unlike slow-scan; Self-Repair fuses redundant rows in MBIST; Test Time predictable cycles vs ATPG vector count.

Conceptual example of BIST usage:

// LBIST Controller + PRPG + MISR for SerDes core
module bist_controller (
  input clk, rst_n, test_mode,
  input [31:0] scan_enable,
  output reg [511:0] signature
);
  reg [6:0] lfsr_state;
  wire prbs_bit;
  reg misr_clk;
  
  // PRPG (LFSR-127 for logic BIST)
  always @(posedge clk) begin
    if (test_mode)
      lfsr_state <= {lfsr_state[5:0], lfsr_state ^ lfsr_state};
  end
  assign prbs_bit = lfsr_state;
  
  // MISR signature compaction (512b poly x^512 + x^11 + x^2 + 1)
  always @(posedge misr_clk) begin
    signature <= {signature[510:0], signature ^ signature ^ prbs_bit};
  end
  
  // Run 10M cycles, compare golden_signature
  // Pass: signature == 512'hDEADBEEF... (precomputed fault-free)
  // Fail: Mismatch indicates stuck-at fault
endmodule

Conceptually, BIST transforms passive silicon into active diagnostic engine—PRPG floods DUT with PRBS, MISR digests responses into compact signature verified against golden reference at power-on or field diagnostics. Production ATE triggers BIST execution in <100ms (vs hours ATPG), enabling 99.9% fault coverage for USB4 PHYs where external probing hits physical limits; self-repair fuses boost yield 5%+ while runtime BIST enables graceful degradation in AI accelerators.