SerDes

/ˈsɜːr dɛs/

n. "Parallel-to-serial transceiver pair enabling high-speed chip-to-chip communication over minimal pins."

SerDes, short for Serializer/Deserializer, converts wide parallel data buses (32-128 bits) into high-speed serial streams over 1-4 differential pairs for PCIe, USB4, and Ethernet backplanes, with TX PISO (Parallel-In Serial-Out) clocking bits via PLL while RX SIPO (Serial-In Parallel-Out) recovers data/clock using CDR. Integrates CTLE, DFE, and LFSR-driven PRBS generators for 112Gbps+ PAM4 links with 1e-6 pre-FEC BER.

Key characteristics of SerDes include: Parallel-to-Serial Conversion reduces 64 PCB traces to 4 differential pairs; Clock Data Recovery extracts embedded timing from serial stream; Equalization Stack combines CTLE (high-freq boost) + DFE (post-cursor cancel); 8b/10b, 64b/66b, or 256b/257b encoding ensures DC balance; Retimers/Redrivers extend reach beyond 30dB loss.

Conceptual example of SerDes usage:

// 32:1 SerDes TX serializer (simplified)
module serdes_tx_32to1 (
  input clk_32x,          // 32GHz for 1Gbps serial
  input [31:0] parallel_in,
  output reg serial_out
);
  reg [4:0] bit_cnt = 0;
  reg [31:0] data_reg;
  
  always @(posedge clk_32x) begin
    if (bit_cnt == 31) begin
      data_reg <= parallel_in;
      bit_cnt <= 0;
      serial_out <= parallel_in;  // LSB first
    end else begin
      serial_out <= data_reg[bit_cnt+1];
      bit_cnt <= bit_cnt + 1;
    end
  end
endmodule

// RX CDR + 1:32 deserializer
module serdes_rx_1to32 (
  input clk_ref, serial_in,
  output reg [31:0] parallel_out,
  output reg clk_1x
);

Conceptually, SerDes shrinks motherboard pin counts from 128+ to <10 by multiplexing bits at 56-112Gbps/lane, validated by BERT stressing DUT through backplanes—PRBS31 patterns confirm CTLE/DFE convergence while CDR locks phase. Powers DisplayPort UHBR20 and USB4 tunneling, where gearbox adapts 64b/66b Ethernet to 256b/257b PCIe encoding for protocol bridges.