/tiː ɑːr siː ˈdiː/
n. — "Row activation to CAS delay—DRAM's 'kitchen ready' timer."
tRCD (Row address to Column address Delay) measures minimum clock cycles between row activation (ACT) and CAS read/write command in DRAM, typically 10-18 cycles where sense amplifiers stabilize the open page before column access. Listed as second timing parameter (CL-tRCD-tRP-tRAS), tRCD governs random access latency (=tRCD+CL) while DDR prefetch hides sequential sins, scaling roughly constant ~13-15ns across generations despite clock inflation.
Key characteristics and concepts include:
- Critical path for row miss → first data: ACT waits tRCD, then CAS waits CL—total random latency benchmark.
- Separate read/write values (tRCDRD/tRCDWR) in DDR4+ reflecting DQS strobe vs command timing differences.
- Bank interleaving hides one tRCD while others process, essential for GDDR shader streams.
- True latency (ns) = cycles × (2000/MT/s), staying ~12-15ns from DDR1 (tRCD=2×500ns) to DDR5 (tRCD=36×0.357ns).
In DDR5 random access, ACT row47 (tRCD=36 cycles=12ns), CAS col3 (CL=36=12ns), data via DQS—repeat across 32 banks while controller chases row hits to dodge full tRCD+CL penalty.
An intuition anchor is to picture tRCD as kitchen prep after ordering: row activation stocks counters (sense amps stable), tRCD waits for organization before waiter (CAS) grabs your plate—rushed prep burns food, idle prep wastes time.