/roʊ/
n. — "DRAM's horizontal data platter that must activate before CAS can serve column snacks."
Row activation (ACT command) in DRAM dumps an entire row's worth of capacitors (~1K-16K cells) onto sense amplifiers via wordline assertion, opening the page for subsequent CAS column reads/writes measured by tRCD latency (row-to-column delay). Measured in clock cycles (tRCD=10-18), row hits skip re-activation for instant CAS while conflicts force tRP precharge + new ACT, crippling bandwidth as controllers chase spatial locality across DDR banks.
Key characteristics and concepts include:
- Wordline assertion connects entire row (~8KB) to bitlines, sense amps latch charge differences—tRCD waits for stable voltages before CAS releases column data.
- Row hit policy keeps hot rows open for back-to-back CAS, row conflict closes (tRP) then reopens (tRCD+CAS)—classic latency vs throughput war.
- Bank-level parallelism hides one row cycle while others cook, critical for GDDR shader traffic pretending random access exists.
- tRAS (row active time) caps how long a row lingers before forced precharge, balancing refresh needs against greedy open-page policies.
In a DDR4 stream, ACT row0 (tRCD=13), CAS col47 (CL=16), CAS col128 (row hit), PRE row0 (tRP=13), ACT row42 (tRCD), CAS col3—repeat across 16 banks while controller predicts the next winning row.
An intuition anchor is to picture DRAM row as a restaurant kitchen: ACT swings open the pantry door dumping ingredients onto counters (sense amps), CAS grabs specific shelves—leaving the pantry open risks spoilage (tRAS), closing/reopening wastes time (row conflict).