/ˌdiː diː ˈɑːr tuː/
n. — "DDR2: DDR1's gym-rat sequel that halved voltage to 1.8V and pretended 4n prefetch made it bandwidth royalty."
DDR2 (Double Data Rate 2) SDRAM drops DDR's 2.5V bloat to 1.8V with 4n prefetch (double DDR1's 2n wimpiness), 400-1066 MT/s data rates, 8 banks, Posted CAS, and on-die termination (ODT) to mock multi-DIMM signal reflections while internal clock runs at half data-bus speed for power savings. Building on DRAM foundations, DDR2 introduces AL (additive latency), write latency = read latency -1, and RDQS strobe for x8 devices, fueling mid-2000s Core 2 Duo glory before DDR3's fly-by wizardry.
Key characteristics and concepts include:
- 4n prefetch architecture bursting four column words per activate to pins, pretending DDR1's 2n was cute at 533-1066MT/s.
- Internal clock at half I/O rate + SSTL_18 signaling slashing power 40% vs DDR1, because 2.5V was so early-2000s.
- Posted CAS (AL) and write leveling pretending memory controllers aren't timing-juggling clowns.
- 8 banks + ODT faking concurrency across 240-pin DIMMs, with burst-8 chopping for sequential bliss.
In a classic dual-channel Northbridge mambo, DDR2 interleaves rank accesses while ODT tames stubs, chasing row hit policies and AL tricks to sustain 8.5GB/s (PC2-6400) until DDR3 fly-by nuked the topology.
An intuition anchor is to picture DDR2 as DDR1 that discovered the gym and diet: double prefetch muscles, voltage cut for stamina, ODT tattoos—strutting twice the bandwidth while mocking its predecessor's power-guzzling flab.