/kæs/
n. — "Clock cycles DRAM waits after row activation before coughing up column data."
CAS (Column Address Strobe) latency measures clock cycles between a DRAM read command and data appearing on pins after row activation opens the page, typically CL=2-3 for DDR1, 14-22 for DDR4, 32-40+ for DDR5 where higher numbers mask faster clocks. Primary DDR timing parameter advertised on specs (CL16-18-18-36 etc.), CAS dominates random-access latency while prefetch depth hides sequential sins, with true latency (ns) = CL × (2000/MT/s).
Key characteristics and concepts include:
- Critical path for random column reads from open pages, where lower CL wins 1:1 latency battles but higher MT/s often wins real-world wars.
- Posted CAS (AL) in DDR2+ pipelines commands ahead, faking lower effective latency through prefetch trickery.
- tCL governs read-to-data-valid window, while tCWL (write CAS) lags reads by 0-2 cycles for write leveling calibration bliss.
- Absolute latency stays ~10-15ns across DDR generations despite CL inflation, because physics hates free speed lunch.
In a DDR5 controller beat, ACT opens row (tRCD), CAS fires after CL=40 cycles (13ns real), data bursts via DQS strobes—repeat 100k+ times/sec while bank groups hide conflicts and refresh steals cycles.
An intuition anchor is to picture CAS as the DRAM receptionist: row activation dials the extension, CAS is hold music duration before data transfer connects—faster receptionists beat longer hold times, even if the office clock sped up.